1. Field of the Invention
The present invention relates to a method for driving a liquid crystal display, a driving circuit of the liquid crystal display, and an image display device and more particularly relates to the method for driving the liquid crystal display, and the driving circuit of the liquid crystal display in which liquid crystal cells are arranged in a matrix form, and the image display device being equipped with the liquid crystal display.
The present application claims priority of Japanese Patent Application No.2000-216621 filed on Jul. 17, 2000, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 10 is a schematic block diagram showing configurations of a driving circuit of a conventional color liquid crystal display 21 disclosed in Japanese Patent Application Laid-open No. Hei 6-295162. The color liquid crystal display 21 is an active-matrix type color liquid crystal display using a TFT (Thin Film Transistor) as a switching element in which each of pixels is placed at an intersection of a plurality of scanning electrodes (gate lines) 22 mounted at specified intervals in a row direction and a plurality of data electrodes (source lines) 23 mounted at specified intervals in a column direction and each of the pixels includes a liquid crystal cell 24 being an equivalent capacitive load, TFT 25, used to drive each of corresponding liquid crystal cells 24 and a capacitor (not shown) used to accumulate a data electric charge during one vertical synchronized period and in which a data red signal, data green signal, and data blue signal generated based on a serial video red signal SR, a serial video green signal SG, and a serial video blue signal SB are applied to the data electrodes 23 and scanning signals generated based on a horizontal synchronizing signal SH and a vertical synchronizing signal SV are applied to the scanning electrodes 22, thus allowing a color character, image, or a like to be displayed.
Moreover, the driving circuit of the conventional color liquid crystal display chiefly includes a controller 31, a serial/parallel converting circuit 32, a gamma converting circuit 33, a data inverting circuit 34, data electrode driving circuits 351 and 352 and a scanning electrode driving circuit 36. The controller 31 generates an upper side horizontal scanning pulse PHU, a lower side horizontal scanning pulse PHD, and a vertical scanning pulse PV based on the horizontal synchronizing signal SH fed from outside and vertical synchronizing signal SV and feeds them to the data electrode driving circuits 351 and 352 and the scanning electrode driving circuit 36 and, at the same time, controls each of the components. The serial/parallel converting circuit 32 has each of serial/parallel converting sections 32a, 32b and 32c (not shown), which corresponds to the serial video red signal SR, the serial video green signal SG, and the serial video blue signal SB all of which are analog signals fed from outside and each of the serial/parallel converting sections 32a, 32b and 32c is adapted to convert the serial video red signal SR, the serial video green signal SG and the serial video blue signal SB, under control of the controller 31, into parallel video red signal SRP, parallel video green signal SGP, and parallel video blue signal SBP. The gamma converting circuit 33 makes a gamma correction to the parallel video red signal SRP, the parallel video green signal SGP, and the parallel video blue signal SBP to provide shades of gray and outputs as a parallel video red signal SRG, a parallel video green signal SGG, and a parallel video blue signal SBG, respectively.
The data inverting circuit 34, in order to drive the color liquid crystal display 21 with alternating current, reverses polarity of a half of each of the parallel video red signal SRG, the parallel video green signal SGG, and the parallel blue signal SBG relative to standard voltages of the data electrode driving circuits 351 and 352 so that the parallel video red signal SRG, the parallel video green signal SGG, and the parallel video blue signal SBG become a negative phase video red signal NSRG, a negative phase video green signal NSGG, and a negative phase video blue signal NSBG respectively and, at the same time, feeds them together with a remaining half of the parallel video red signal SRG, the parallel video green signal SGG, and the parallel video blue signal SBG to the data electrode driving circuits 351 and 352 by switching between these signals every time one line is written. The data electrode driving circuits 351 and 352, with timing of the upper side horizontal scanning pulse PHU and the lower side horizontal scanning pulse PHD being fed from the controller 31, generates a data red signal from either of the parallel video red signal SRG or the negative phase video red signal NSRG, a data green signal from either of the parallel video green signal SGG or the negative phase video green signal NSGG, and a data blue signal from either of the parallel video blue signal SBG or the negative phase video blue signal NSBG and feeds them to each of corresponding data electrodes 23 of the color liquid crystal display 21. The scanning electrode driving circuit 36, with timing of the vertical scanning pulse Pv fed from the controller 31, generates a scanning signal and applies it to each of the corresponding scanning electrodes 22 of the color liquid crystal display 21.
FIG. 11 is a circuit diagram showing configurations of a serial/parallel converting section 32a making up the serial/parallel converting circuit 32 in the conventional color liquid crystal display 21. The serial/parallel converting section 32a shown in FIG. 11 is made up of a shift register 41, 2n-pieces (n is an integer being 2 or more) of sample holding circuits 421 to 422n and n-pieces of selectors 431 to 43n and converts the serial video red signal SR into n-pieces of parallel video red signals SRP1 to SRPn. The shift register 41 is a serial-in/parallel-out type shift register made up of 2n-pieces of delay flip-flops (DFF) and performs a shifting operation to shift a start pulse STP fed from the controller 31, in synchronization with a shift clock SCK fed from the controller 31, and simultaneously outputs each bit of 2n bits of parallel data as sampling pulses SP1 to SP2n to each of the sample holding circuits 421 to 422n. Each of the sample holding circuits 421 to 422n, based on each of the corresponding sampling pulses SP1 to SP2n each being fed from the shift register 41, samples each of voltages SR1 to SR2n of the serial video red signal SR and holds each of the sampled voltages SR1 to SR2n of the serial video red signal SR for specified period of time. Moreover, though each value of the voltages SR1 to SR2n in a present period is actually different from each value of the voltages SR1 to SR2n in a next period, since it is output from the same sample holding circuit 42, a same symbol is assigned to these values. Each of the selectors 431 to 43n, based on a selector control signal SCTL fed from the controller 31, outputs either of the voltages SR1 to SRn Of the serial video red signal SR fed from the corresponding sample holding circuits 421 to 42n or voltages SR(n+1) to SR2n of the serial video red signal SR fed from the corresponding sample holding circuits 42n+1 to 422n as each of the parallel video red signals SRP1 to SRPn.
Moreover, configurations of the serial/parallel converting sections 32b and 32c (not shown) are the same as those of the serial/parallel converting section 32a except that the signals input and output are different, therefore description of the serial/parallel converting section 32b and 32c are omitted.
Next, operations of the serial/parallel converting section 32a will be described by using a case as an example in which n=4, that is, eight pieces of the sample holding circuits 421 to 428 and four pieces of the selectors 431 to 434 are mounted in the serial/parallel converting section 32a, by referring to the timing chart shown in FIG. 12. First, the shift register 41, when the start pulse STP (not shown) and shift clock SCK (shown in FIG. 12(1)) are fed from the controller 31, performs shifting operations to shift the start pulse STP in synchronization with the shift clock SCK and outputs each bit of 2n-bit parallel data as sampling pulses SP1 to SP8 (shown in FIG. 12(3) to FIG. 12(10)).
Therefore, when the analog and serial video red signal SR (shown in FIG. 12(2)) is fed from outside, the sample holding circuit 421, while the sampling pulse SP1 is high, samples a voltage SR1 of the serial video red signal SR and, then, while the sampling pulse SP1 is low, holds the voltage SR1 of the sampled video red signal SR. Though the serial video red signal SR is an analog signal, in FIG. 12(2), to simplify description, each of the voltages SR1 to SR8 is expressed as if they were digital data.
Similarly, the sample holding circuit 422, while the sampling pulse SP2 shown in FIG. 12(4) is high, samples a voltage SR2 of the serial video red signal SR and then, while the sampling pulse SP2 is low, holds the voltage SR2 of the sampled video red signal SR. The sample holding circuit 423, while the sampling pulse SP3 shown in FIG. 12(5) is high, samples a voltage SR3 of the serial video red signal SR and then, while the sampling pulse SP3 is low, holds the voltage SR3 of the sampled video red signal SR. The sample holding circuit 424, while the sampling pulse SP4 shown in FIG. 12(6) is high, samples a voltage SR4 of the serial video red signal SR and then, while the sampling pulse SP4 is low, holds the voltage SR4 of the sampled video red signal SR.
Next, when the selector control signal SCTL is changed to be high in synchronization with a fifth rise of the shift clock SCK as shown in FIG. 12(11), the selectors 431 to 434, based on the selector control signal SCTL at a high level, by connecting each of common terminals Tc to a first terminal T1, during periods being surrounded by broken lines shown in the left part of FIGS. 12(3) to (6) and outputs the voltages SR1 to SR4 of the serial video red signal SR held by each of the corresponding sample holding circuits 421 to 424 as the parallel video red signals SRP1 to SRP4.
Next, the sample holding circuit 425, while the sampling pulse SP5 is high shown in FIG. 12(7), samples a voltage SR5 of the serial video red signal SR and then holds, while the sampling pulse SP5 is low, the voltage SR5 of the sampled video red signal SR. Similarly, the sample holding circuit 426, while the sampling pulse SP6 is high shown in FIG. 12(8), samples a voltage SR6 of the serial video red signal SR and then holds, while the sampling pulse SP6 is low, the voltage SR6 of the sampled video red signal SR. The sample holding circuit 427, while the sampling pulse SP7 is high shown in FIG. 12(9), samples a voltage SR7 of the serial video red signal SR and then holds, while the sampling pulse SP7 is low, the voltage SR7 of the sampled video red signal SR. The sample holding circuit 428, while the sampling pulse SP8 is high shown in FIG. 12(10), samples a voltage SR8 of the serial video red signal SR and then holds, while the sampling pulse SP8 is low, the voltage SR8 of the sampled video red signal SR.
Next, when the selector control signal SCTL is changed to be low in synchronization with a ninth rise of the shift clock SCK as shown in FIG. 12(11), the selectors 431 to 434, based on the selector control signal SCTL at a low level, by connecting each of the common terminals Tc to a second terminal T2, during periods being surrounded by the broken lines shown in the left part of FIGS. 12(7) to (10), outputs the voltages SR5 to SR8 of the serial video red signal SR held by each of the corresponding sample holding circuits 425 to 428 as the parallel video red signals SRP1 to SRP4.
Operations described above are sequentially repeated at four-clock intervals of the shift clock SCK. Operations for the serial video green signal SG and serial video blue signal SB are the same as those for the above serial video red signal SR.
The reason why such the serial/parallel converting circuit 32 is mounted in a driving circuit of the conventional liquid crystal display described above is as follows. That is, in ordinary cases, operation speeds of the data electrode driving circuits 351 and 352 are lower than that of the controller 31, the gamma converting circuit 33 and the data inverting circuit 34. For example, in a case of a liquid crystal display called an SXGA (Super Extended Graphics Array)-type liquid crystal display which has a resolution of 1280×1024 pixels, though frequency of an operating clock of the controller 31 or a like, that is, the frequency of an analog and serial video signal fed from outside is 135 MHz, the frequency of the operating clock of the data electrode driving circuits 351 and 352 is about 20 MHz. To solve this problem, by converting the serial video signal having high frequencies, that is, with high resolution, into the parallel video signal so that simultaneous and parallel processing can be performed even in low-speed data electrode driving circuits 351 and 352, operation speeds of the data electrode driving circuits 351 to 352 to a frequency characteristic of a video signal with high resolution fed from outside are matched. Such the signal processing in which the serial video signal is converted into the parallel video signal is called “phase expansion” in a sense that one signal with high frequencies is expanded so as to become a plurality of signals of phases with low frequencies. For example, in the case of the SXGA-type liquid crystal display, by expanding the serial video signal fed from outside so as to become the signal of eight phases, the frequency is changed to be 16.875 MHz (135 MHz/8 phases), which enables the data electrode driving circuits 351 and 352 with their operation speeds of about 20 MHz to successfully perform signal processing.
In a recent advanced state of multimedia, high definition is required in a liquid crystal display including compatibility with a photo or a printed matter of extremely high resolutions and a liquid crystal display called a UXGA (Ultra Extended Graphics Array)-type liquid crystal display which has a resolution of 1600×1200 pixels has been developed. In the UXGA-type liquid crystal display, the frequency of the serial video signal fed from outside is 162 MHz. Therefore, even if this serial video signal is phase-expanded so as to become a signal of eight phases, the frequency becomes 20.25 MHz (162 MHz/8 phases), thus almost reaching an operational limit of the data electrode driving circuits 351 to 352. Therefore, if timing of rising and falling of the sampling pulses SP1 to SP8 is the same as that of rising and falling of the selector control signal SCTL, the following inconvenience occurs. That is, if, for example, as shown by “a” in FIG. 12(6), the selector 434 is switched just during the settling time while the sample holding circuit 424 is sampling the voltage SR4 of the serial video red signal SR based on the sampling pulse SP4 at a high level, due to much settling time being time required for a voltage of a capacitor to reach within tolerance on an input voltage caused by a capacitance of the capacitor making up each of the sample holding circuit 421 to 428 and/or due to the timing in which the selector control signal SCTL rises earlier than the sampling pulse SP falls which is caused by a delay in signal transmission induced by routing of wirings, noise that should not be displayed appears on the color liquid crystal display 21, which causes inconsistencies in displaying. More particularly, if the selector 434 is switched earlier, though the voltage SR4 of the serial video red signal SR is at a white level, than the capacitor making up the sample holding circuit 424 is charged sufficiently by the voltage SR4 being at the white level, a part of the pixels is displayed in slightly darkish red on the liquid crystal display 21 (when the serial video green signal SG and the serial video blue signal SB are at a black level). The operations shown by “a” in FIG. 12(10) are the same as described above.
In contrast to the above, for example, as shown by “b” in FIG. 12(1), though the sample holding circuit 421 has already started sampling the voltage SR1 due to delayed switching speed of the selector 43 and/or due to the timing in which the selector control signal SCTL falls later than the sampling pulse SP rises which is caused by a delay in signal transmission induced by routing of wirings, if the selector 431 has not yet been switched, noise that should not be displayed on the liquid crystal display 21 as inconsistencies in displaying on the liquid crystal display 21. More particularly, when the voltage SR1 of the serial video red signal SR sampled during the present period is at a black level and the voltage SR1 of the serial video red signal SR to be sampled during a next period is at a white level, though the sample holding circuit 421 has started sampling the voltage SR1 of the serial video red signal SR at a white level, if the selector 431 has not yet been switched, part of the pixels is displayed in slightly bright red on the color liquid crystal display 21 (when the serial video green signal SG and the serial video blue signal SB are at a black level). The operations shown by “b” in FIG. 12(7) are the same as described above.
Conventionally, such the inconsistencies in displaying are resolved by finely calibrating the timing of rising or falling of the selector control signal SCTL and some inconsistencies in displaying are tolerated. However, in the UXGA-type liquid crystal display, since the data electrode driving circuits 351 and 352 are operated in a state almost reaching its operational limit, it is difficult to resolve such the inconsistencies in displaying and the inconsistencies exceed its tolerated limit. To solve this problem, a measure of increasing the number of the phases to be applied to the phase expansion may be proposed, however, it presents problems in that the number of the selector required for one color of the video signal is increased by the number of the increased phases and the number of the sample holding circuits is also increased by twofold numbers of the increased number of the phases, thus causing increased costs of the driving circuits of the liquid crystal display. Moreover, routing of wiring required for providing signals of so many phases to the driving circuit is made complicated and driving circuits of the liquid crystal display become large in size accordingly. Additionally, since an influence by delay in signals caused by the routing of the wiring cannot be neglected, it is impossible to solve the problem only by finely calibrating rising and falling of the selector control signal SCTL.
On the other hand, in ordinary cases, since the data electrode driving circuits 351 and 352 and the scanning electrode driving circuit 36 are constructed of integrated circuits (IC) and, in recent years, the ICs are manufactured by using polysilicon which has high on-resistance and low operation speed in many cases, they cannot satisfactorily handle the serial video signal having high frequencies in the liquid crystal display with high definition. Moreover, in order to achieve miniaturization of the liquid crystal display, technology is being developed in which the data electrode driving circuits 351 and 352 and the scanning electrode driving circuit 36 are fabricated using polysilicon on a glass substrate on which the liquid crystal display is formed. In this case, the on-resistance of the switching device making up each of the driving circuits is made larger than that in the ordinary ICs and the operation speed is made lower, needs for a method and circuits to satisfactorily handle the video signal with high frequencies in the liquid crystal display with high definition.